20GSps 6-bit Low-Power Rad-Tolerant ADC, Phase I

The proposed project aims to develop a 20GSps 6-bit radiation hardened analog to digital converter (ADC) required for microwave radiometers being developed for space and air borne earth sensing applications. Aiming to improve performance and to reduce the size of the electronics, high resolution, high-sampling rate, power efficiency and low spur energy are the requirements for ADCs employed for direct digitization in microwave radiometers. The proposed 20GS/s 6-bit interleaved successive approximation (SAR) ADC is intended to achieve >5 ENOB and 20GHz input bandwidth. A number of innovations will be introduced to the ADC in order to combine low power consumption with high signal to noise and distortion (SINAD), and spurious free dynamic range (SFDR) which is important for spectrography applications. A novel low glitch energy technique coupled with interleaved samples aperture calibration will be introduced to achieve digitization accuracy, improve linearity and achieve high sampling rate. The proposed ADC ASIC will contain on-chip all necessary components, including a frequency synthesizer, serial interface, standard interface with an FPGA, and design-for-testability features. The ADC will be implemented using a deep submicron CMOS technology. The project's Phase I will provide the proof of feasibility of implementing the proposed ADC. Phase II will include finishing design, fabrication, testing and delivering the ADC prototypes which will be ready for commercialization in Phase III.