High-Rate Receiver Design, Phase I
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High-Rate Receiver Design, Phase IHTML
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High-Rate Receiver Design, Phase IHTML
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High-Rate Receiver Design, Phase IHTML
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High-Rate Receiver Design, Phase IHTML
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| Field | Value |
|---|---|
| Groups |
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| Tags |
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| isopen | False |
| license_id | us-pd |
| license_title | us-pd |
| maintainer | TECHPORT SUPPORT |
| maintainer_email | hq-techport@mail.nasa.gov |
| metadata_created | 2025-11-29T23:39:21.648597 |
| metadata_modified | 2025-11-29T23:39:21.648601 |
| notes | We propose an initial architectural and preliminary hardware design study for a high-rate receiver capable of decoding modulation suites specified by CCSDS 413.0-G-1 April 2003 (www.ccsds.org) and new advanced modulation suites. We propose to detail a design which can provide a throughput of greater than 300 Mbits/sec and 7 bits/sample output. |
| num_resources | 4 |
| num_tags | 8 |
| title | High-Rate Receiver Design, Phase I |