Bringing 3D Memory Cubes to Space: a "Rad-Hard by Design Study" with an Open Architecture, Phase II

The computing capabilities of onboard spacecraft are a major limiting factor for accomplishing many classes of future missions. Although technology development efforts are underway that will provide improvements to spacecraft CPUs, they do not address the limitations of current onboard memory systems. In addition to CPU upgrades, effective execution of data-intensive operations such as terrain relative navigation, hazard detection and avoidance, autonomous planning and scheduling, and onboard science data processing and analysis require high-bandwidth, low-latency memory systems to maximize processor usage (the ?memory wall?) and provide rapid access to observational data captured by high-data-rate instruments (e.g., Hyperspectral Infrared Imager, Interferometric Synthetic Aperture Radar). 3D ICs, after a long wait, is now a reality. The first mainstream product is 3D memory cubes, where multiple memory tiers (4 DRAM tiers as of 2015) are vertically integrated to offer manifold improvement in size, capacity, speed, and power consumption compared with 2D counterparts. Indeed, these are the memory parts that will truly enable aforementioned missions. Unfortunately, none of these are ready for space. The purpose of this research is to investigate the challenges and opportunities in deploying 3D memory cubes into space missions.